1. Field of the Invention
The present invention generally relates to the field of communication with different peripherals in an information technology system.
More particularly, the present invention applies to the field of programmable integrated circuits of the type comprising a microprocessor, microprocessor peripherals and an interconnect bus to connect the peripherals to the microprocessor. In the context of the present invention, the term microprocessor peripheral signifies any programmable integrated circuit device separate from the central processing unit (microprocessor) to which it is linked and which may provide data input and output. In particular, it relates to peripherals that communicate with external system components.
2. Discussion of the Related Art
In the industrial domain, certain communication peripherals require the prior configuration of communications, which must be implemented before the communication is initiated. Typically, this step involves initializing peripheral control registers with data concerning speed, the number of bits per character transmitted or other types of information depending on the type of protocol used to access the peripheral.
For example, in the context of the SPI (Serial Peripheral Interface) protocol, a microcontroller is provided to communicate with several peripherals through a single serial link; each peripheral is connected to the SPI bus by a peripheral selection line, referred to as a “chip select” line, used to select one of several peripherals. Thus, before initiating a data exchange on the SPI bus with a peripheral, the microcontroller must first configure the chip select register of the peripheral with which it wishes to communicate. Other control registers relating, for example, to clock configuration information, may also be initialized during the data exchange.
In addition, within the context of the LIN (Local Interconnect Network) protocol, the LIN bus must also be configured before a communication with a LIN peripheral can begin. In particular, it is first necessary to send a header on the bus containing the features of the message, for example the number of octets to be transmitted, the transfer direction, etc.
Thus, before initiating a data exchange with this type of SPI- or LIN-compatible peripheral, a number of configuration operations must be implemented. This operating mode, therefore, makes this type of peripheral unsuitable for system architectures intended for sending data directly from a peripheral to the memory, or from the memory to the peripheral, using a DMA (Direct Memory Access)-type controller, which makes it possible to directly access the memory without going through the processor.
In fact, in this context of direct transfer, as shown in FIG. 1, the microprocessor 1 first initializes the DMA communication by sending the DMA controller 2 the transfer starting address, the length of the data and the transfer direction, and then it launches the transfer. The DMA controller 2 then takes control of the memory 5 and the input/output controller 3 of the peripheral 4. The data transfer can then be performed without going through the processor.
However, the DMA controller is not intended to perform the initialization operations of the peripheral control registers, which must be configured before initiating any exchange of data.
In fact, direct access transfer to the memory allows a peripheral to “borrow from the memory” of the system in order to use it as a buffer zone, that is, as a temporary storage area, thereby making it possible to rapidly save data as they are input or output. To do so, a memory location, tagged by a starting address and an end address, is assigned to the peripheral so it can exchange data with the system according to the method for directly accessing the memory, without involving the microprocessor.
According to the example in FIG. 2, a communication peripheral therefore has registers R0 to R4, implemented at fixed memory addresses. Registers R0, R1 and R3 are intended to be control registers that must be configured before initiating a data exchange. For example, register R0 is a register containing the bit rate information, register R1 is a register containing the “chip select” information, and register R3 is a register containing the clock configuration information. Register R2 is the data transmission register and register R4 is the data reception register. These registers are implemented at fixed memory addresses.
Moreover, as also shown in FIG. 2, when the DMA controller implements a DMA data transfer from the memory to a peripheral, the transfer is typically performed from variable memory addresses: address_i, address_i+1, . . . , which self-increment (or self-decrement), to a fixed memory address corresponding to the address of the peripheral transmission register R2.
Therefore, it is clear that it is impossible for the DMA controller to collect, in one single operation, the initialization phase for the peripheral control registers and the actual phase of data transfer to the transmission register. In fact, the initialization phase for control registers R0, R1 and R3 of the peripheral 4 forces pointing to memory addresses, which are not contiguous. However, the DMA controller is unable to perform such an operation. The standard DMA controller is only intended to perform a variable address transfer to a fixed address from the memory to the peripheral or a fixed address (corresponding to the address of reception register R4) transfer to variable memory addresses that will be incremented, from the peripheral to the memory.
Since the peripheral control registers are stored to non-sequential addresses, establishing a data exchange with this type of peripheral whose control registers must first be initialized involves additional preliminary work by the main processor to initialize these registers before the relay can be passed to the DMA controller for the actual data transfer. Performance, in terms of processor usage time, is thus degraded by this preliminary step of control register initialization carried out by the processor.